As semiconductor devices provided by modern semiconductor technology continue to scale down in size, critical dimension variation across a semiconductor wafer can significantly affect the production yield and electrical performance of the devices fabricated on the wafer. A high percentage of the critical dimension variation is caused by “line edge roughness” resulting from lithographic processing of the semiconductor wafer. “Line edge roughness” refers to variations that occur along an edge of a patterned feature as a result of semiconductor wafer processing. To understand the specific causes of line edge roughness, power spectral density for an edge of a patterned feature, such as a transistor gate, can be determined and utilized to analyze the distribution of line edge roughness in the “frequency domain.”
In the present application, “frequency domain” refers to the summation of frequencies into which line edge roughness can be resolved. Line edge roughness is typically measured in a spatial dimension, such as length of deviation from a reference line. However, the variations that occur along the length of an edge of a patterned feature, i.e. the line edge roughness, can be represented as a summation of different frequency components, i.e., the “frequency domain” of the line edge roughness.
In a conventional approach, line edge roughness can be represented in the frequency domain by determining power spectral density for an edge of a patterned feature by utilizing a fast Fourier transform algorithm. In the conventional approach, line edge roughness is typically measured by using a tool such as a scanning electron microscope. However, since the scanning electron microscope has limited sampling length and resolution, the power spectral density determined by the fast Fourier transform algorithm includes a large amount of noise, which undesirably reduces the accuracy of the line edge roughness represented by the power spectral density.